The present invention relates to a data reproducing apparatus, and, more particularly, to a data reproducing apparatus which reproduces data recorded on a recording medium, such as an optical disk or magnetic disk.
As shown in FIG. 1, data is recorded on an optical disk in units of sectors each comprising an ID section 1 and a data section 2. The data section 2 includes sync patterns SB1 to SB3, a plurality of resync patterns RS1 to RS39, a user data section 3, an error checking or cyclic redundancy check (CRC) code storage section (not shown) and an error correcting code (ECC) storage section 4.
In case of reading data from an optical disk, the ID section 1 is read prior to reading of the data section 2 and the address of the sector is checked based on data in the ID section 1, then reading of the data section 2 is started. When the sync patterns SB1 to SB3 and the resync patterns RS1 to RS39 are read, data in the user data section 3, the error checking code and error correcting code are read synchronously using those marks and are stored in a buffer memory.
When reading one sector of data is finished, error correction is performed on the sector data using the error checking code and error correcting code and read data is reproduced. The reproduced data is stored again in the buffer memory. The reproduced data stored in the buffer memory is output via a host interface.
The sync patterns SB1 to SB3 and the resync patterns RS1 to RS39 can be detected when detection window setting signals ws1 and ws2 are set to high (H) levels in their respective time widths Tw1 and Tw2.
In a case where the sync patterns SB1 to SB3 could not be detected in the H-level period of the detection window setting signal ws1, data D1 to D15 recorded between the sync patterns SB1 to SB3 and the resync pattern RS1 cannot be read. In this case, a sync miss detection signal SMS is set to an H level and dummy data of “00h” is stored in the buffer memory in place of the unreadable data D1 to D15 before the detection window setting signal ws2 is set to an H level.
Next, when the resync pattern RS1 is read in the H level period of the detection window setting signal ws2, a resync pattern detection signal RSS is generated. Then, reading of data D16 to D512 in the user data section 3 is started in accordance with the resync pattern detection signal RSS and those data are stored in the buffer memory. The dummy data D1 to D15 of “00h” stored in the buffer memory are restored through an error correction process after reading of the sector is finished and the dummy data is replaced with the restored data in the buffer memory.
As shown in FIG. 2, the data reproducing apparatus includes a signal processing unit 100 which performs the above-described data reproducing process and a buffer memory 13. The signal processing unit 100 includes an MPU interface unit 5, an internal processor 6, a disk interface 7, a host interface 8, an error correcting operation unit 9 and a data transfer control circuit 10, which are mutually connected via an internal control bus 11, and a speed matching buffer 12 connected to the disk interface 7. The data transfer control circuit 10 includes an error correcting circuit 14, a data transfer circuit 15 and a memory controller 16.
The MPU interface unit 5 mutually transfers control signals with an MPU in a system control unit (not shown). The internal processor 6 performs the general control of the signal processing unit 100 in accordance with firmware stored in a program ROM 6a. 
At the time of data reproduction, the disk interface 7 receives read data DR of an optical disk from a drive head (not shown) and discriminates based on data in the ID section 1 of each sector whether a target sector has been read. In a case where the target sector has been read, the disk interface 7 reads data in the user data section 3 using the sync patterns SB1 to SB3 and the resync patterns RS1 to RS39 in the data section 2 and supplies the data to the speed matching buffer 12 and the error correcting operation unit 9.
The disk interface 7 detects if each of the sync patterns SB1 to SB3 has been read. In a case where the sync patterns have not been detected (in a case where reading of the sync patterns has failed), the disk interface 7 supplies the sync miss detection signal SMS to the data transfer control circuit 10 and stops supplying data to the speed matching buffer 12 until the resync pattern RS1 is detected next.
At the time of writing data, the disk interface 7 supplies write data Dw to the drive head.
The speed matching buffer 12 is preferably an FIFO (First-In-First-Out) memory and supplies data supplied from the disk interface 7 to the data transfer control circuit 10 in a byte-by-byte manner at the time of data reproduction. At the time of writing data, the speed matching buffer 12 supplies write data supplied from the data transfer control circuit 10 to the disk interface 7.
At the time of data reproduction, the data transfer control circuit 10 stores data supplied from the speed matching buffer 12 in the buffer memory 13. In response to the sync miss detection signal SMS, the data transfer control circuit 10 generates dummy data corresponding to user data between the sync patterns SB1 to SB3 and the resync pattern RS1 and stores the dummy data in the buffer memory 13.
At the time of data reproduction, the error correcting operation unit 9 receives the read data DR from the disk interface 7 and performs an operation using one sector of user data, the error checking code and error correcting code to generate error position data EP and error quantity data EQ. Error correction is a known scheme disclosed in, for example, Japanese Laid-Open Patent Publication No. 8-137624.
The data transfer control circuit 10 receives the error position data EP and error quantity data EQ from the error correcting operation unit 9, generates reproduced data by performing error correction on one sector of read data stored in the buffer memory 13 and rewrites corresponding data stored in the buffer memory 13 with the reproduced data. The reproduced data is read from the buffer memory 13 and is supplied to an external unit via the data transfer control circuit 10 and the host interface 8.
The error correcting circuit 14 includes an EOR circuit 17 and a register 18. The register 18 receives the error position data EP from the error correcting operation unit 9 after reading of each sector data is finished and supplies the error position data EP to the buffer memory 13 as an address signal ADR1 via the memory controller 16. The EOR circuit 17 receives data DTi read from the buffer memory 13 according to the address signal ADR1 and the error quantity data EQ supplied from the error correcting operation unit 9, and performs an EOR operation on the data DTi and the error quantity data EQ. The EOR circuit 17 supplies EOR operation data DTo which is error-corrected data to the associated address of the buffer memory 13. Data stored in the buffer memory 13 is rewritten with error-corrected data in this manner.
The data transfer circuit 15 includes a sequencer 19, a counter 21, a dummy data generating circuit 22, a first selector 23, a second selector 20, a first address holding circuit 24, a register 25 and an adder 26.
The sequencer 19 supplies a control signal SG2 to the second selector 20 based on read position information supplied from the disk interface 7 and supplies a count start signal CT to the counter 21 in response to the sync miss detection signal SMS.
The counter 21 starts a counting operation in response to the count start signal CT and supplies a count signal SG1 to the dummy data generating circuit 22 and the first selector 23.
Dummy data Dd or “00h” is supplied to the first selector 23 from the dummy data generating circuit 22 and the read data DR is also supplied to the first selector 23 from the speed matching buffer 12. The first selector 23 outputs the dummy data Dd in response to the count signal SG1 and outputs the read data DR when the count signal SG1 is not supplied.
The first address holding circuit 24 receives an address from the internal processor 6, holds the address and supplies the held address to the second selector 20. The address is for storing the data D1 immediately after the sync patterns SB1 to SB3 in the data section 2 in the buffer memory 13.
The second selector 20 first selects an output signal S1 from the first address holding circuit 24 based on the sync miss detection signal SMS, then selects an output signal S2 from the adder 26 as shown in FIG. 4.
The output signal of the second selector 20 is supplied as an address signal ADR2 to the buffer memory 13 via the register 25 and the memory controller 16. The address signal ADR2 is for storing the read data DR or the dummy data Dd in the buffer memory 13.
The address signal ADR2 output from the register 25 is supplied to the adder 26. The adder 26 adds “1” to an address value of the address signal ADR2 and supplies the resultant address to the second selector 20.
In a case where the sync patterns SB1 to SB3 are properly read at the time of reading the data section 2, the error correcting circuit 14 and the data transfer circuit 15 write the read data DR in the buffer memory 13 using the header address held in the first address holding circuit 24. In a case where the sync miss detection signal SMS is supplied, the dummy data Dd is stored in the buffer memory 13 using the header address held by the first address holding circuit 24. Next, when the resync pattern RS1 is read, the read data DR is stored in the buffer memory 13.
When reading of one sector is finished, data is read from the buffer memory 13 based on the error position data EP, and the read data is subjected to error correction by the error correcting circuit 14, so that data stored in the buffer memory 13 is rewritten with the error-corrected data.
For data recording/reproducing apparatuses that perform an operation of writing data onto a recording medium using a laser, a scheme has been proposed which changes the write start position in the data section 2 at random in order to suppress fatigue of the recording medium caused by the repetitive writing operation to the recording medium.
Because the write positions for the sync patterns SB1 to SB3 and the resync patterns RS1 to RS39 change at random in this scheme, it is necessary to make the time widths Tw1 and Tw2 of the detection window setting signals ws1 and ws2 long in order to read the sync patterns SB1 to SB3 and the resync patterns RS1 to RS39. In this case, it is desirable that the time widths Tw1 and Tw2 should be made long to such a length that the detection window setting signals ws1 and ws2 overlap each other. It is however necessary to finish writing of dummy data in the buffer memory before the detection window setting signal ws2 goes to a high level after the detection window setting signal ws1 falls to a low level. It is not therefore possible to make the time widths Tw1 and Tw2 of the detection window setting signals ws1 and ws2 sufficiently long. This makes it impossible to adequately cope with a change in the write start position in the data section 2.